1. Field of Invention
The present invention relates to a DRAM, and more particularly to a method of forming a contact hole of a DRAM.
2. Description of the Prior Art
A DRAM is an element in semiconductor processing that is formed by a large number of single transistors and is a combination of DRAM memory cells. Each DRAM memory cell is formed by a metal oxide semiconductor (MOS) transistor connected in series to a capacitor. Each MOS transistor and capacitor is electrically connected by several word lines and bit lines to determine the address of every memory cell. The DRAM controls the opening and closing of the channel between the source and drain by controlling the voltage of the word line and generating "0" and "1" signals in the memory cell.
When the memory cell has a relatively high voltage a "1" signal is generated and the PN junction of the MOS transistor's drain on the substrate connected to the capacitor is unstable. In time, the capacitor will start to leak current. Therefore, the charge of the memory cell has to be refreshed cyclically if the voltage is to be maintained, otherwise current may leak causing the storage signal of "1" in the memory cell to fall to "0".
Please refer to FIG. 1. FIG. 1 is a drawing of the structure of the memory cell 10 of a stack DRAM according to the prior art. A memory cell 10 of the DRAM is formed on a semiconductor wafer and comprises a Si substrate 12, a MOS transistor 14 on the Si substrate, a dielectric layer 16 position on the Si substrate 12 and the MOS transistor 14, two bit lines 18 within the dielectric layer 16 for transmitting information, a capacitor 20 for storing the charge and data, and a word line 22 for interconnecting the memory cells. The capacitor comprises an fieldplate 24 formed by doped poly-silicon as its upper layer, a storage node 26 as its lower layer and an interposed unit cell dielectric layer 28 with an oxide-nitride-oxide (ONO) structure between the field plate 24 and the storage node 26.
In the formation of the memory cell 10, the first step is to form the MOS transistor 14, dielectric layer 16 and two bit lines 18 on the Si substrate 12. Then, a contact hole 21 is formed within the dielectric layer 16 to be used as a node contact for the storage node 26 of the capacitor 20. The contact hole 21 is formed vertically along the side walls of the two bit lines 18 while removing the dielectric layer 16 to the surface of the MOS transistor 14. A silicon oxide layer 25 is then formed on the side walls of the two bit lines 18 followed by formation of a spacer 23 made of silicon nitride on the contact hole 21. The spacer 23 serves as an electrical insulating layer between the storage node 26 and the bit line 18 and prevents electrical connection between the capacitor 20 and bit line 18. This in turn prevents leakage of current. Lastly, the contact hole 21 is cleaned and the storage node 26, the ONO dielectric layer 28 and the field plate 24 are formed. This completes the production of the capacitor 20 and memory cell 10.
The cleaning solution used to clean the contact hole 21 may etch the exposed silicon oxide layer 25 in the contact hole 21 causing breakdown of the insulation between the storage node 26 and bit lines 18. Further, the spacer 23 of the contact hole 21 is in direct contact with the drain on the Si substrate 12. However, since the spacer 23 and the Si substrate 12 have different thermal expansion coefficients, thermal stress occurs in the contact region of the spacer 23 and the Si substrate 12 causing leakage of current in the PN junction on the Si substrate. This effect reduces the capability of storage charge of the capacitor 20 and increases the refresh frequency of the signal of the memory cell 10 so as to reduce the performance of the stack DRAM.